For most (I really hope all) experienced designers this is obvious, but hopefully this saves some beginners effort and most importantly time (and some money, too)
I cover actually two different things here, but they are somewhat related so I'll go ahead with this anyway.
When designing the board it usually goes from schematic to layout - electrical drawing to board layout. In schematic you design the connections between the components, and in layout you "just" need to place chips and draw the traces on board. Should be easy. At this point I hear experienced folks giggling, it never is that easy. The last few traces are always the worst - typically you'd have to run a trace from one end of the board to the other end, but the board is already full. So you sigh, put it where it fits (in process ripping up dozens of already placed traces, just to route them tighter together to make some room) and hope it won't look too bad. And hopefully it works too, without generating or receiving too much noise (hope you were smart enough to design those delicate analog parts first...)
Like I said, typical work flow. From schematic to layout. Especially common in larger companies where schematic and layout people may not even speak to each other at any point (in my opinion that is Really Bad, but that's just how it is).
Lately I've found out that this actually is pretty bad flow in practice. How, exactly, are you supposed to know in schematic what is the optimum for the layout? With "fixed-function" (I mean: every pin of chip has one and only one function, like op-amp) chips it's easy, but with MCUs it already grows more difficult as you can assign some signals almost any pin you want to.
Above is part of my current board under construction (I use EagleCAD. By now I'm used to it, so I have no real desire to re-learn everything if I were ever to change so I'd rather keep using it, despite its shortcomings).
Chip here is a FPGA, which are nice, allowing just about any signal placed in almost any pin. And on this board there are lots of signals, making routing a real fun job (you may notice some overlap - this board uses blind vias so those actually are okay).
But returning to my earlier argument, here the "schematic first-layout last" - design would fail really badly. If you were to naively design schematic first, placing all signal there with no care of the pin (well, pad), layout design would get really, really ugly. So here I chose to place components first, then route easy parts and only then connect FPGA and final (high-ish-frequency, many many signals around the board) components.
As a side note, this makes dual-monitor setup very very useful - whatever I'm primarily working on is in primary monitor and other has datasheet (although I often still prefer paper, but that's another topic) or schematic (when designing layout) or other helpful material on it.
So here I started going around. "I want a pin to control this component, what pin is closest?". Pick a BGA pad, connect to component, then draw on layout. Then pick next component clockwise and do same again. And again. And again, many many times. And finally I have pretty nice fanout, with fairly low effort spent.
Then to another issue: ERC and DRC. I know that first instinct often is to run those after design is done, see that they produced lots of errors and then ignore it. DON'T. EVER. DO. THAT. Really, never ignore those. You will suffer if you do. Both of these tools are there for a reason - they catch design errors. Not all of them are "real" errors but many will be, so do not ever ignore any of them before careful consideration.
So when schematic is done, run ERC first. This will generate many non-errors; non-connected pins (they may be pins you don't need, unused inputs and outputs and whatnot), overlapping nets, nets crossing without junction and so on. Lots of stupid errors, yes? No. Hidden there are real errors; pin that seems to have wire connected but doesn't; connected nets that aren't and so on. Fix them (or make your tool ignore them), all of them, and only then then proceed to layout.
So on layout the DRC. Again, there will be errors. Some may be false errors, your chip might have pads very close to each other so the default clearance makes DRC fail. Then you must fix your design rules' settings (and remember that tighter clearance may raise the board cost too) and run again.
Soon you start hitting real errors; overlapping nets, places where signal are too close together, actually cross and so on, the real errors. Some of marked errors may still be false, but DRC usualy allows you to mark there ones permanently ignored so they don't show up later. Real errors you will of course need to fix. And eventually your DRC will show no errors either.
But never, ever send your boards for manufacturing before both your ERC and DRC both report no errors. If you ignore them, you will regret it. And don't worry, even with those errors cleared, there will be sufficient amount of errors on your board anyway, especially if you are just starting as designer. But that's okay, that's how we learn. Assemble your board, fix errors on next layout and carry on. Next one will be better.
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